Designing Using Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. Verilog is most commonly used in the design, verification, and implementation of digital logic chips at the Register transfer level (RTL) level of abstraction.
You will find free Verilog resources in the KnowHow
section of our website.
Doulos has set the industry standard for Verilog training since it delivered one of the world's first independent classes in 1992. Since then, over 500 companies across the world have chosen Doulos' Verilog design expertise to get their engineers project-ready, enhance their design skills and improve productivity.
- Train using the tools of your choice
Because Doulos is an independent company, you benefit from learning Verilog using the EDA tools of your choice. And because we aren't aligned to any particular vendor, you'll learn coding styles that maximise the portability of code between EDA tools, rather than approaches tuned to a particular tool. (Unless of course we're delivering in-house training, in which case the training is tailored to your specific design context). Tools supported by these courses include:
- Aldec Active HDL™ & Riviera-PRO™
- Cadence Incisive®
- Mentor Graphics ModelSim® & Questa®
- Synopsys VCS®
- Synopsys Synplify Pro®
- Synopsys Design Compiler®
- Mentor Graphics Precision® RTL
- Get the best project reference material
We've all been on a training class that squeezes too much detail on to a slide, jumps around the subject, and supplies class notes that you can't easily reference after the class.....Doulos training materials are not like that! Tutor's notes accompany the slides, an index makes them an excellent project reference, and our famous Verilog Golden Reference Guide has 198 pages packed with syntax, hints, tips and practical advice. Doulos training materials really are sought after references in their own right.
- Learn faster and more easily
Doulos tutors make learning easier, faster, and enjoyable! Experienced design engineers themselves, they combine a talent for teaching with indepth understanding and experience of real world design issues and solutions. And, drawing on nearly 20 years of Doulos' corporate training experience, our tutors really know what it takes to create and deliver effective training.
- Customize in-house training to match your requirements
Doulos excels at tailoring in-house training to meet your exact training needs - including tool and technology focus. You'll find us very easy to work with - flexible, professional and with a guarantee of the expert technical interaction you need to ensure you get the best for your team, and the most from your budget.
- Essential Digital Design Techniques
Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL class. With a strong emphasis on practical design and hands-on workshops, this class has been developed to significantly cut the on-the-job learning curve by capturing design techniques usually learned over months, in an intensive 2-day class.
- Fast-track Verilog for VHDL Users
Fast-track Verilog for VHDL Users is an intensive 2-day conversion-training course teaching the application of the VerilogÂ® Hardware Description Language for programmable logic and ASIC design. It is suitable for engineers who have already attended the Comprehensive VHDL course or are well practised in VHDL based design.
- Comprehensive Verilog
Comprehensive Verilog has been the industry's gold standard Verilog training class since 1992 because it's the fastest, most effective way to get project-ready. You'll gain the expertise you need to write efficient, re-usable RTL code, and create test benches powerful enough to cope with complex designs.
- Expert Verilog
Expert Verilog teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. Presented in two distinct modules, this 4 day intensive class focuses on language and synthesis issues, design re-use, test benches and the latest verification techniques. Each module also includes an overview of the 2001, 2005 and SystemVerilog extensions to Verilog, with an assessment of their impact on both design and verification
Expert Verilog Design (days-1-2) teaches you to write better, more efficient code that is easier to maintain and re-use. Design for verification is also covered with an introduction to assertion-based techniques using the delegate's choice of SVA or PSL.
Expert Verilog Verification (days 3-4) shows you how to speed up and improve design verification; make testbench writing easier and more effective; design testbenches with flexibility and re-use in mind; and create behavioural models to make your testbenches more realistic and more productive.
- Comprehensive SystemVerilog
Based on the Verilog® hardware description language, the SystemVerilog language extensions enhance Verilog in a number of areas, providing productivity improvements for RTL designers, verification engineers and for those involved in system design and architecture. Comprehensive SystemVerilog addresses the needs of both design and verification groups and includes objective and up-to-date commentary on the two best-known published verification methodology approaches, and teaches the key SystemVerilog language features that support them.
- Essential Perl
Perl is a widely-used cross-platform programming language, which is especially valuable to engineers targeting ASICs and and large FPGAs. Perl's process, file, and text manipulation facilities, in particular, enable skilled users to achieve a range of productivity boosting short-cuts, and avoid easy-to-make mistakes that are time consuming to fix. Essential Perl, unlike other Perl classes, is focused on the needs of EDA users. It covers the essential subset of the Perl5 scripting language and is packed with design related exercises and examples including: patching netlists, filtering reports, generating test vectors, and running tools.
- Essential Tcl/Tk
Tcl/Tk is a powerful way to manage your design process, automate otherwise error-prone and time-consuming tasks and achieve valuable gains in efficiency and productivity. Every VHDL user and EDA support specialist needs to know about Tcl. Unlike the numerous Tcl text books and classes available, the Doulos Essential Tcl/Tk class is focused on the needs of EDA users, and it's packed full of examples and exercises directly based on design related problems.
Doulos Project Services is a powerful resource giving your company rapid access to expertise for direct use on project issues. A wide range of packages exist to assist you through all stages of methodology and language decision making, integration and design use. All our packages can be provided with the flexibility to provide support exactly when required, maximising the benefit to cost ratio.
Designing Using SystemVerilog
SystemVerilog is the first industry-standard language covering the requirements of both design and verification. It provides the benefits of broad capability in all areas of design and verification, with the advantage of a widely supported IEEE standard spanning project generations.
In line with the demands for finely tuned training programs for application to both design and verification contexts, Doulos has created an enhanced portfolio:
Doulos is uniquely qualified to give you the complete view of SystemVerilog's capabilities in any tool context. Doulos SystemVerilog training encapsulates:
- comprehensive expertise
full scope training and project support
- corporate independence
broad tool & methodology support, plus unbiased tuition
- co-operative long-standing relationships with the key vendors
up-to-date knowledge and complete client support packages
Not only have we been delivering SystemVerilog training and project support since the early days of the language (2004), we've worked with the verification methodology groups in Cadence, Mentor Graphics and Synopsys throughout SystemVerilog's evolution. Our SystemVerilog expertise is authoritative. Based on a deep understanding of the language, the methodologies, and what it takes to get SystemVerilog out of the box and applied to real-world projects, Doulos is expert in developing and customizing effective SystemVerilog training.
These are just some of the companies our in-house SystemVerilog expertise has helped to get SystemVerilog out of the box.
- Mentor Graphics
Unbiased tuition using your chosen tool and methodology. Because we're comercially independent and don't have a vested interest in selling you a particular product, Doulos is the ideal language and methodology training partner. Big decisions demand an independent perspective.
This is a one-stop solution addressing the needs of both design and verification groups. It includes objective and up-to-date commentary on the three best-known published verification methodology approaches, and teaches key SystemVerilog language features that support them.
The key to its success (and that of our clients' subsequent SystemVerilog-based designs) is our careful handling of what many consider a difficult topic, class-based SystemVerilog verification. This is a critical part of the SystemVerilog learning path. If it isn't taught well, engineers will take much longer to put what they've learned into practice, and find SystemVerilog much harder than it actually is. Doulos has leveraged years of experience in teaching object-oriented verification concepts to make these challenging topics easier to learn for engineers from a wide variety of backgrounds. This makes the Doulos class the ideal preparation for subsequent adoption of a sophisticated verification methodology such as UVM, OVM or VMM (which are covered in our UVM, OVM and VMM Adopter classes). More >>
Verilog & SystemVerilog Courses