Each vendor tool supplies libraries containing packages for VHDL simulation, and often a tool or script to compile these. This section summarises what each package does.
VITAL Gate Level Simulation
VITAL gate level simulation uses some standard libraries from the IEEE, together with vendor specific libraries, as follows:
You won't need to do anything, they are built-in to all simulators.
For Actel, you'll need to compile the appropriate package for the particular type of chip you are using. For a ProASIC3 you'll need
Compile this package into a library called proasic3. You'll also find the low level Verilog models in the same folder, if you're using Verilog.
For Altera, you'll need to compile the appropriate packages for the particular chip type you are using. For instance, with Cyclone, you need to compile
into a library called cyclone.
For Lattice, you need to compile a particular library according to the chip technology you are using. For instance, for an ECP series device, you would compile the files in the folder path_to_ispLever\cae_library\simulation\vhdl\ecp\src\
into a library called ecp.
For certain tools, you'll find a compile script in the same directory, which you can use directly, or use as the basis for your own compile script.
For Xilinx, all device technologies are supported by a common set of packages known as SIMPRIMS (simulation primitives). You can create the library by compiling these files, which can be found in the directory %XILINX%\vhdl\src\simprims
into a library called simprim. There are also some simulation vendor versions of these libraries in the same directory.
The technology vendors supply simulation libraries that let you simulate technology primitives in your design. For instance, you can instance a single look-up table and simulate it. Synthesis tools understand these instances and will synthesize correctly. Note that these libraries are not timing accurate like the VITAL libraries.
For Actel, the sames libraries are used as for VITAL (see above). If you have compiled the required files for a particular technology such as ProASIC3, you can make instances of primitive components from that technology.
For Altera, there is a set of packages called altera_mf (Altera Megafunctions) which contain models of varying complexity. The files are in "the usual place", that is
You should compile these into a library called altera_mf .
Lattice users can use the same files as shown for VITAL above, again compiled per device technology.
Xilinx users have a library UNISIM (Unified Simulation) which contains behavioral models for low level components. The code is situated in
Compile the files in this order, into a library called unisim
High Level Behavioral Models
Some vendors require different libraries and packages to be used for high level models, that is primarily models created by an IP Generator. These packages are documented below.
Actel users can just use the same (device specific) models mentioned above. These will allow you to simulate models generated by Actel Smartgen.
Altera users will generally only need the altera_mf library and packages. These will allow simulation of MegaWizard generated components. There is another Altera modelling system which is not used so much nowadays, known as LPM (Library of Parameterizable Models). LPM was in fact an industry standard, but never really became very popular. If you need to simulate LPM models, you will need to compile the files:
into a library called LPM.
Lattice models generated by IP Express will simulate correctly using the device specific libraries mentioned above.
Xilinx Core Generator models need the library XilinxCoreLib. You need to compile the following files many files contained in the directory:
The easiest way to do this is to use the Xilinx compxlib script, which is documented in the Xilinx Development System Reference - or simply type:
at a command prompt.
Compiling Simulation Libraries
Generally compiling libraries just uses the same techniques you use for compiling any VHDL or Verilog code. However there are a few hints depending on which tool you are using.
Simulation libraries can be compiled using the tool compxlib which is easy to use - just type:
at a command prompt.
It is also possible to launch the same tool from the ISE GUI. The basic steps are:
- Highlight your project in the Sources for: pane
- Set Sources for: to Behavioral Simulation
- Now in the Processes pane click the + next to Design Utilities
- Right click on Compile HDL Simulation Libraries and select Processes...
- Set up the required tool, language, and library details and click OK
- Double click Compile HDL Simulation Libraries and wait for compilation to complete
When you install Aldec Active-HDL, you may at the same time install pre-compiled libraries for various FPGA technologies. These are available as a separate download from the Aldec web-site.
One thing to note - each version of Aldec Active-HDL provides libraries compiled against a particular version of the FPGA Vendor tools; so you may find that you don't always have the latest Vendor library versions if you don't keep your Active-HDL completely up-to-date.
If you find this, there is nothing to stop you compiling the FPGA vendor simulation libraries by hand.
Xilinx won't accept my OFFSET IN/ OFFSET OUT constraints
This is something that happens a lot on training courses, but is simple to fix.
The following screen shot shows the constraint editor in Xilinx ISE
On courses, people encounter two problems with this form:
- You must not enter a time unit - if you wan't a time of 10 ns, just type 10 on its own.
- If you type in 10 and then close the form, sometimes the value will not be noticed. To make sure the value is taken, click somewhere outside the text entry box (for instance on the grey background of the form) before closing the constraint editor.